imec: Breakthroughs in ferroelectric memory research for next-generation storage solutions to meet the data demands of the AI era

imec, a world-leading research and innovation center for advanced semiconductor technologies, presents two advances in ferroelectric memory research, targeting both ferroelectric capacitors and ferroelectric field-effect transistors as promising candidates for enabling low-voltage operation and high integration density. Ferroelectric memory is gaining increasing attention as AI applications place unprecedented pressure on memory systems to deliver more capacity, higher bandwidth, and better energy efficiency at an affordable cost. As conventional memory technologies such as DRAM and SRAM become increasingly difficult to scale, ferroelectric approaches are emerging as promising candidates because they can combine low-voltage operation with the potential for denser 3D integration. Against this backdrop, imec is presenting two complementary advances: low-voltage ferroelectric capacitors that could support future DRAM-like memory, as well as vertically stacked FeFETs that pave the way for compact, high-density memory architectures for next-generation AI systems.

It has been shown that by reducing the thickness of the ferroelectric layer, ferroelectric capacitors enable low-voltage operation (~1.3 V) while maintaining high residual polarization (>40 μC/cm²) and a long lifespan (≥10¹³ cycles)—key requirements for DRAM-like memory applications. In a separate demonstration, imec takes a step toward high-density 3D ferroelectric memory using vertically stacked, IGZO-based ferroelectric field-effect transistors (FeFETs). The work presents the first functional demonstration of a vertical stack of FeFET memory cells with five word lines, thereby increasing memory density by stacking the devices on top of one another. By introducing a dual-gate configuration with a back gate, imec improves erase performance—a key challenge for FeFET technology. This architectural innovation underscores the potential of oxide-based FeFETs for future high-density memory applications.

It is imec’s multidisciplinary approach that brings together the presented device concepts through shared materials, integration strategies, and a common vision for realizing scalable 3D ferroelectric memory. Both approaches rely on similar ferroelectric material stacks, whereby insights from interface optimization and scaling in capacitors are directly transferable to the optimization of FeFET devices. At the same time, the advanced 3D integration techniques demonstrated for FeFET stacking open up new avenues for realizing high-density 3D arrays of ferroelectric capacitors. Both memory devices—ferroelectric capacitors and FeFETs—offer distinct advantages, with insights from one area driving further optimization of the other.

These advances come at a critical juncture for the semiconductor industry. As memory technologies such as DRAM and SRAM are reaching their scaling limits and AI-driven workloads require exponentially larger memory capacities, the need for new memory concepts is becoming increasingly urgent. The proven low-voltage operation of ferroelectric capacitors supports energy-efficient memory concepts, while vertically stacked FeFETs pave the way for compact, high-density memory suitable for embedded and future computing architectures. Taken together, these innovations offer complementary approaches to addressing the performance and cost challenges in future data-centric systems.

“This work demonstrates how imec’s multidisciplinary expertise—ranging from materials science to advanced 3D integration—enables us to tackle some of the most pressing challenges in memory technology,” said Attilio Belmonte, program director at imec. Maarten Rosmeulen, Program Director at imec, continues: “We are exploring various paths toward the memory solutions that will be required to sustain the rapid growth of AI and data-intensive applications.”

Looking ahead, imec will continue to refine both device concepts while addressing remaining challenges, such as the endurance and erase performance of FeFETs, as well as further voltage scaling and reliability optimization for ferroelectric capacitors. Future work will focus on evaluating these technologies at the system level, developing fully integrated 3D memory architectures, and improving key performance metrics to bring these concepts closer to practical implementation. Although these results are still in the research stage, they represent important steps toward next-generation memory technologies that could redefine how data is stored and retrieved in the AI era.

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