“Design your custom RISC-V SoC with the Silicon-Proven Scale4Edge Flow” – Register for the Scale4Edge Roadshow Day in Dresden on 5 June 2025

"Design your custom RISC-V SoC with the Silicon-Proven Scale4Edge Flow"

Register for the Scale4Edge Roadshow Day in Dresden on 5 June 2025

We are excited to invite you to the "Scale4Edge Roadshow Day" taking place on 5 June 2025, at Dorint Hotel Dresden, Germany.

We look forward to receiving your registration by 21 May 2025 at » https://eveeno.com/scale4edge-roadshow

Scale4Edge Roadshow Day

"Design your custom RISC-V SoC with the Silicon-Proven Scale4Edge Flow"

Agenda

Time Duration Item Person

09:00 00:15 Welcome to Scale4Edge Prof. Dr. Wolfgang Ecker (Scale4Edge Project Coordinator,

Distinguished Engineer, Infineon Technologies AG,

Honorary Professor TU Munich)

09:15 00:30 RISC-V Overview Stefan Wallentowitz (Munich University of Applied Sciences)

09:45 00:45 Early performance evaluation to identify hotspots Eyck-Alexander Jentzsch (MINRES Technologies GmbH)

10:30 00:30 Break

11:00 00:45 Implementing ISAX in RISC-V using CoreDSL Tammo Mürmann and Markus Scheck (TU Darmstadt)

11:45 00:45 Developing a platform using Scale4Edge Florian Kriebel (MINRES Technologies GmbH)

12:30 01:00 Lunch

13:30 00:45 Integrating AI accelerators into the platform Paul Palomero Bernardo (Eberhard Karls Universität Tübingen)

14:15 00:45 Tailoring a SW toolchain for the platform Jan Schlamelcher (German Aerospace Center (DLR))

with TU Darmstadt and TU Munich

15:00 00:30 Break

15:30 00:45 Deployment and Benchmarking of Edge AI Models Philipp van Kempen (TU Munich)

16:15 00:45 RTOS for customised SoCs Anton Paule (FZI Forschungszentrum Informatik)

with SYSGO GmbH

17:00 End of Scale4Edge Roadshow

Scale4Edge is a collaborative effort that brings together a selection of excellent universities, research institutes, and industrial partners. We aim to significantly reduce the development time and cost of application-specific edge components. Our approach is based on providing a commercial RISC-V ecosystem for a scalable and flexibly extensible edge computing platform. On our one-day roadshow, we provide an insight into the platform and its features, highlighting the tools and methods developed within the Scale4Edge project from an application-driven perspective. We demonstrate how your target application can be analysed, integrated, executed and optimised using the versatile silicon-proven Scale4Edge ecosystem. In short, our roadshow provides a compact and comprehensive demonstration of how the Scale4Edge ecosystem can be used to rapidly develop application-specific edge components.

We start the roadshow with a short introduction to the Scale4Edge project and the open, royalty-free instruction set architecture RISC-V, showing their strong features and benefits. Based on an example application, we then demonstrate an instruction set simulator-based approach for early performance evaluation and code hotspot identification. Building on this foundation, we present the design and description of customised performance-enhancing ISA extensions for RISC-V using CoreDSL, a behavioural architecture description language. We use the extension descriptions to generate hardware modules that we integrate into a target RISC-V core using the SCAIE-V extension interface. Following this, we embed this customized RISC-V core into a generator-based subsystem. It forms the ecosystem platform, which is highly configurable in terms of RISC-V core, bus system and peripherals. We further extend this platform by integrating generator-based AI accelerators, demonstrating its versatility and ability to handle complex workloads. We then pivot to the development and customisation of accompanying software toolchains by first integrating the custom ISA extensions into a compiler toolchain. As AI workloads play an important role in today's systems, we follow up with deployment of AI models on our edge devices. Finally, we show how to integrate and run a real-time operating system (RTOS) on a customised SoC prototype.

Reasons for Attending

Our roadshow provides a practical and application-oriented introduction to the methods and tools developed in the Scale4Edge project, demonstrating the complete development flow from application to successful execution on an edge computing platform. This includes insights into application profiling, ISA extension development, platform building, integration of AI capabilities, compiler toolchain and RTOS support. The roadshow provides an excellent opportunity to discuss and network with experts in RISC-V, AI and edge computing to quick-start your journey to your application-specific RISC-V SoC.

Target Audience

Embedded system and SoC developers, AI engineers, and hardware/software developers.

Scale4Edge is funded by the German ministry of education and research (BMBF) (reference numbers: 16ME0122K-16ME0140+16ME0465) as part of the programme „Future-proof Special Processors and Development Platforms (ZuSE)". The authors are responsible for the content of this publication.

Registration deadline: 21 May 2025

We look forward to receiving your registration »

For details/questions, see below or get in touch with us,

writing to: voerg@edacentrum.de

We look forward to welcoming you to Dresden!

Best regards,

Andreas Vörg (Scale4Edge Office)