Microelectronics

Renesas: Agreement signed with Honda to develop a high-performance SoC for software-defined vehicles

January 9, 2025. Honda Motor Co., Ltd. and Renesas Electronics Corporation announced on January 9 that they have signed an agreement to develop a high-performance system-on-chip (SoC) for software-defined vehicles (SDVs). The new SoC is designed to deliver top-class AI performance*1 of 2,000*2 TOPS combined with best-in-class energy efficiency of 20 TOPS/W and will be used in future models of the “Honda 0 (Zero) Series”, Honda’s new electric vehicle series, especially those to be launched in the late 2020s. The agreement was announced on January 7 at a Honda press conference at CES 2025 in Las Vegas, Nevada.

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Honda Senior Managing Executive Officer, Katsushi Inoue and Renesas SVP Vivek Bhan. Photo: Renesas

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Honda is developing original SDVs to deliver a mobility experience optimized for each individual customer in the Honda 0-Series. The Honda 0-Series will adopt a centralized E/E architecture that combines multiple electronic control units (ECUs) responsible for controlling vehicle functions into a single ECU. The central ECU, which serves as the heart of the SDV, manages essential vehicle functions such as Advanced Driver Assistance Systems (ADAS) and Automated Driving (AD), powertrain control and comfort functions – all on a single ECU. To achieve this, the ECU needs an SoC that offers higher processing performance than conventional systems while minimizing power consumption.

Renesas is committed to providing semiconductor solutions for the automotive industry that enable car manufacturers to develop SDVs. Renesas’ R-Car solutions offer higher AI performance with the ability to customize by leveraging multi-die chiplet technology*3 and integrating AI accelerators*4 into the SoC.

To realize Honda’s vision for SDVs, Honda and Renesas have reached an agreement to develop a high-performance SoC computing solution for centralized ECUs. By utilizing TSMC’s leading 3nm process technology for the automotive industry, this SoC can also achieve a significant reduction in power consumption. In addition, a system that uses multi-die chiplet technology to combine Renesas’ fifth-generation (Gen 5) generic R-Car X5 SoC series with an AI accelerator optimized for Honda’s independently developed AI software will be realized. With this combination, the system is expected to achieve one of the industry’s best AI performance with energy efficiency. The SoC chiplet solution will provide the AI performance required for advanced functions such as AD while maintaining low power consumption. The chiplet technology allows the flexibility to create customized solutions and offers future upgrades for feature and performance improvements.

Honda and Renesas have worked closely together for many years. This agreement will accelerate the integration of advanced semiconductor and software innovations into the Honda 0-Series and improve the mobility experience for customers.

*1 Renesas estimate as of January 2025
*2 Tera Operations Per Second (TOPS) is a metric for AI processing performance and measures the number of operations that can be performed per second. Based on a sparse AI model.
*3 Technology for building a system by combining multiple chips with different functions
*4 Hardware designed for high-speed and high-efficiency AI (artificial intelligence) computing

The contents of the press release, including but not limited to product pricing and specifications, are based on the information as of the date stated in the document, but are subject to change without notice.

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Further links

👉 www.renesas.com

Photo: Renesas

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