The advanced process design kits (PDKs) from the NanoIC pilot line play a key role in driving innovation in the semiconductor sector. They provide designers with early access to realistic design rules and implementation workflows long before hardware for a new technology is available. With the introduction of the A14 and eDRAM PDKs, NanoIC is giving designers early insight into two important technology areas for future computer systems for the first time: logic scaling at the A14 Angstrom node and embedded memory integration.
By making these PDKs freely accessible, NanoIC aims to connect early-stage design research with real-world integration, helping researchers and start-ups explore new nodes, anticipate integration challenges and evaluate designs against realistic scaling metrics. “PDKs like A14 and eDRAM are catalysts for learning and design,” explains Marie Garcia Bardon, head of department at imec and work package leader in the NanoIC project. “They provide a robust environment for practical evaluation and quantitative comparison of different technology options. This approach accelerates learning, reduces the risks of architecture and design innovation, and helps designers prepare for advanced logic nodes and embedded memory technologies long before the hardware is available.”
“By making these PDKs widely accessible, we are lowering the barriers for universities, industry and start-ups to engage with next-generation technologies,” continues Giuseppe Fiorentino, program manager for NanoIC. “Access to realistic rules and workflows will allow teams to explore new research directions and breakthrough concepts that will feed directly into the European semiconductor value chain.”
A14 Pathfinding PDK: Scaling down to the 14 angstrom node
As the first of the newly launched PDKs, the A14 Pathfinding PDK provides a virtual design environment for exploring scaling to the 14 angstrom node, one of the next big steps in device miniaturization. A key innovation in this node is the introduction of a direct backside contact as a new scaling accelerator. While the previous N2 PDK supported backside power supply through TSV middle (TSVM) structures, the A14 node evolves this concept by replacing TSVM with a more compact direct backside contact scheme. By delivering power directly from the backside of the wafer to the gates and eliminating complex metal wiring on the topside, this architecture reduces IR waste and offers an 18% area savings and a 7% power reduction compared to N2 at the same frequency and cell density.
Imec is the first company to release a PDK for this node. The kit includes a comprehensive 162-SDC library and is supported by two major EDA vendors, Cadence and Synopsys.
eDRAM system exploration PDK: Enabling embedded memory exploration
Complementing the logic pathfinding work enabled by the A14 PDK, the NanoIC pilot line also introduces a first-of-its-kind eDRAM system exploration PDK, an important step toward addressing one of the biggest challenges in advanced systems: delivering dense, low-latency on-chip memory. Central to this effort is bringing memory closer to processing units, a key strategy for reducing latency and improving energy efficiency in advanced computing architectures.
The current eDRAM PDK provides a virtual platform for exploring embedded memory solutions that bridge the gap between dense but power-hungry off-chip DRAMs and fast but area-limited on-chip SRAMs. With a focus on system-level behavior in data-intensive and AI workloads, it enables researchers to evaluate new memory architectures and integration strategies that bring higher density memory closer to processors and GPUs, reducing traffic, improving power efficiency and increasing overall system performance.
In the future, the eDRAM PDK will evolve into a full system exploration platform. In this next phase, designers will be able to go beyond virtual validation and analyze full system-level interactions. As the platform matures, future development steps will include hardware validation and eventually tape-out and prototyping capabilities on the NanoIC pilot line.
Access and training opportunities
Both PDKs, along with the previously launched N2 PDK, are available through Europractice. To promote adoption and hands-on exploration, NanoIC will host a dedicated workshop on the N2 and A14 PDK on March 25 and 26, 2026 and a workshop on the eDRAM PDK on May 26, 2026. These workshops will provide hands-on guidance, technical insights and direct interaction with the development teams. Full practical details and registration can be found on the NanoIC website.
This work was made possible in part by the NanoIC pilot line. Its acquisition and operation are jointly funded by the Chips Joint Undertaking through the European Union’s Digital Europe (101183266) and Horizon Europe (101183277) programs and by the participating countries Belgium (Flanders), France, Germany, Finland, Ireland and Romania.
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Further links
👉 www.imec-int.com
Photo: imec
